1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile ferroelectric memory in which one cell has a structure of 1T/1C/1R to enable high speed access operation and efficiently prevent a reference cell from being degraded.
2. Discussion of the Related Art
A background art nonvolatile ferroelectric memory will be described with reference to the accompanying drawings.
FIG. 1 is a hysteresis loop of a typical ferroelectric. FIG. 2 is a circuit diagram illustrating a background art ferroelectric memory.
Generally, a ferroelectric memory, that is, ferroelectric random access memory (FRAM) has received much attention for use in a next generation memory device. The ferroelectric memory has processing speed as much as DRAM (dynamic random access memory) used in a semiconductor memory device, and retains data even in the event of power-off. The FRAM which has the almost same structure as the DRAM is a memory device in which data are not erasable even if electric field is removed using high residual polarization characteristic of a ferroelectric used as a material of a capacitor.
In other words, as shown in hysteresis loop of FIG. 1, the polarization organized by the electric field is maintained at a constant amount (d, a state) without extinction due to spontaneous polarization even if the electric field is removed. For application of a memory device, d, a correspond to 1, 0, respectively.
The background art nonvolatile ferroelectric memory device, in general, includes a main memory cell block 1 and a reference cell block 2. The background art nonvolatile ferroelectric memory device includes a sensing amplifier/bitline control block 3 for reading out data of the main memory cell block 1 using the reference cell block 2.
The aforementioned background art nonvolatile ferroelectric memory device will be described in detail.
The main memory cell block 1 includes first and second wordlines WL1 and WL2, a first cell transistor MN1 whose gate is connected to the first wordline WL1 and one electrode is connected to a bitline Bit_line, a second transistor MN2 whose gate is connected to the second wordline WL2 and one electrode is connected to a bit bar line BitB_line, a first ferroelectric capacitor FC1 whose first electrode is connected to the other electrode of the first transistor MN1 and second electrode is connected to a cell plate line PL1, and a second ferroelectric capacitor FC2 whose first electrode is connected to the other electrode of the second transistor MN2 and second electrode is connected to the cell plate line PL1.
The reference cell block 2 includes first and second wordlines WL1 and WL2, a reference transistor RN1 whose gate is connected to the second wordline WL2 and one electrode is connected to the bitline Bit_line, a second reference transistor RN2 whose gate is connected to the first wordline WL1 and one electrode is connected to the bit bar line BitB_line, a first reference ferroelectric capacitor RFC1 whose first electrode is connected to the other electrode of the first reference transistor RN1 and second electrode is connected to a plate line PL1, and a second reference ferroelectric capacitor FRC2 whose first electrode is connected to the other electrode of the second reference transistor RN2 and second electrode is connected to the plate line PL1.
The sensing amplifier/bitline control block 3 includes a bitline control block and a sensing amplifier block. The bitline control block includes first and second NMOS transistors N1 and N2 whose gates are in common connected to a bitline control signal input terminal PBL, one electrodes are connected to the bitline and the bit bar line, respectively, and the other electrodes are connected to a ground terminal Vss, and third, fourth and fifth NMOS transistors N3, N4 and N5 whose gates are in common connected to a bit bar line control signal input terminal EBL. The sensing amplifier block includes first and second PMOS transistors P1 and P2 whose one electrodes are in common connected to a sensing amplifier PMOS enable signal input terminal SAP, and sixth and seventh NMOS transistors N6 and N7 whose one electrodes are in common connected to a sensing amplifier NMOS enable signal input terminal SAN.
Source and drain of the fifth NMOS transistor N5 are connected to the bitline and the bit bar line, respectively.
One electrodes of the third and fourth transistors N3 and N4 are in common connected to a precharge signal input terminal Vcc/2 and the other electrodes thereof are connected to the bitline and the bit bar line, respectively.
Gates of the first PMOS transistor P1 and the sixth NMOS transistor N6 and the other electrodes of the second PMOS transistor P2 and the seventh NMOS transistor N7 are in common connected to the bit bar line.
Gates of the second PMOS transistor P2 and the seventh NMOS transistor N7 and the other electrodes of the first PMOS transistor P1 and the sixth NMOS transistor N6 are in common connected to the bit line.
Data sensing operation of the background art nonvolatile ferroelectric memory device will be described below.
If a low signal is applied through the bitline control signal input terminal PBL, the bitline and the bit bar line are separated from the ground voltage Vss.
If a wordline driving signal W/L is applied at high level, a data signal output from the first ferroelectric capacitor FC1 is transmitted to the bitline Bit_line. At this time, a data signal output from the second reference ferroelectric capacitor RFC2 of the reference cell is transmitted to the bit bar line BitB_line.
The sensing amplifier block amplifies voltage difference between the bit line and the bit bar line. The bitline and the bit bar line are equalized by Vcc/2, so that a voltage at both ends of the first and second ferroelectric capacitors FC1 and FC2 becomes 0V. Further, the wordline becomes Vss level, and the bitline and bit bar line become Vss level if a high signal is applied through the bitline control signal input terminal PBL.
The background art nonvolatile ferroelectric memory device has several problems.
At a standby mode, a node cn1 and a node cn2 become floating state. Therefore, a memory voltage of the nodes cn1 and cn2 drops to 0V due to junction leakage or PL1 voltage is maintained at Vcc/2. This applies inverse bias to the ferroelectric capacitor, thereby resulting in that stored data are lost. To avoid such data loss, there must be provided a circuit for compensating a voltage of a node within the memory cell and a compensating cycle.